Learning hardware using multiple-valued logic - Part 1: Introduction and approach

M.A. Perkowski, D. Foote, Qihong Chen, A. Al-Rabadi, L. Jozwiak

    Research output: Contribution to journalArticleAcademicpeer-review

    9 Citations (Scopus)

    Abstract

    The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation
    Original languageEnglish
    Pages (from-to)41-51
    Number of pages11
    JournalIEEE Micro : Chips, Systems, Software and Applications
    Volume22
    Issue number3
    DOIs
    Publication statusPublished - 2002

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