Large-scale graphene transistors with enhanced performance and reliability based on interface engineering by phenylsilane self-assembled monolayers

Z. Liu, A.A. Bol, W. Haensch

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89 Citations (Scopus)
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Abstract

In this letter, we report the dielectric/graphene interface physics and engineering of large-scale, chemical vapor deposited (CVD) graphene transistors by self-assembling a molecular-scale organosilane monolayer onto the dielectric surface. We show that phenyl-alkyl-terminated self-assembled monolayers (SAM) at the dielectric/graphene interface consistently improve the graphene device performance and reliability. The extrinsic field-effect mobility of large-scale CVD graphene transistors on the phenyl-SAM engineered dielectric is currently up to 2500 cm2/(V s) at room temperature, considerably higher than the counterparts without the SAM. In addition, significant reduction on the bias stress instability and hysteresis is achieved by the SAM-based interface engineering. Further analysis reveals that charge injection from graphene to the dielectric/graphene interface dominates the observed hysteresis behavior. For both graphene transistors with and without SAMs, the bias stress stability, that is, Dirac point shift under bias stress, is well described by the stretched exponential model with its fitting parameters clearly indicating different interface properties
Original languageEnglish
Pages (from-to)523-528
JournalNano Letters
Volume11
Issue number2
DOIs
Publication statusPublished - 2011

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