Large-image CNN hardware processing using a time multiplexing scheme

J. Pineda de Gyvez, Lei Wang, E. Sanchez-Sinencio

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    Abstract

    The state of the art work in cellular neural networks (CNN) has concentrated on VLSI implementations without really addressing the "systems level". While efficient implementations have been reported, no reports have been presented on the use of these implementations for processing large complex images. The work hereby presented introduces a strategy to process large images using small CNN arrays. The approach, time-multiplexing, is prompted by the need to simulate hardware models and test hardware implementations of CNN. For practical size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware processors and all the pixels in the image involved. This paper presents a practical solution by processing the input image block by block, with the number of pixels in a block being the same as the number of CNN processors in the hardware. Image processing results obtained from an actual IC test-chip prototype using this scheme are presented
    Original languageEnglish
    Title of host publicationProceedings of the Fourth IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA-96, 24-26 June 1996, Sevilla, Spain
    Place of PublicationNew York
    PublisherInstitute of Electrical and Electronics Engineers
    Pages405-410
    ISBN (Print)0-7803-3261-X
    DOIs
    Publication statusPublished - 1996

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