Abstract
A robust self-interleaving mechanism for parallel hysteresis current controlled inverters is proposed, with sustained switching under all load conditions. A fast interleaving technique that can be applied for normal load conditions is combined with a self-interleaving mechanism, which ensures correct switching during voltage clamping operation. A minimum switching frequency and maximum duty cycle is guaranteed under all load conditions enabling the use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reduced volume of the passive components and better dynamic response. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple parallel modules. Simulations were conducted to verify the combined operation of both methods and measurements were performed on a 3 kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller.
Original language | English |
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Title of host publication | Proceedings of the 2010 International Power Electronics Conference (IPEC) |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 2822-2829 |
Number of pages | 8 |
ISBN (Electronic) | 978-1-4244-5393-1 |
ISBN (Print) | 978-1-4244-5394-8 |
DOIs | |
Publication status | Published - 2010 |
Event | 2008 International Conference on Power Electronics Conference (IPEC 2010) - Sapporo, Japan Duration: 21 Jun 2010 → 24 Jun 2010 |
Conference
Conference | 2008 International Conference on Power Electronics Conference (IPEC 2010) |
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Abbreviated title | IPEC 2010 |
Country/Territory | Japan |
City | Sapporo |
Period | 21/06/10 → 24/06/10 |