Interleaved switching of parallel ZVS hysteresis current controlled inverters

J.M. Schellekens; J.L. Duarte; M.A.M. Hendrix; H. Huisman

doi:10.1109/IPEC.2010.5543891

Interleaved switching of parallel ZVS hysteresis current controlled inverters

J.M. Schellekens, J.L. Duarte, M.A.M. Hendrix, H. Huisman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

206 Downloads (Pure)

Abstract

A robust self-interleaving mechanism for parallel hysteresis current controlled inverters is proposed, with sustained switching under all load conditions. A fast interleaving technique that can be applied for normal load conditions is combined with a self-interleaving mechanism, which ensures correct switching during voltage clamping operation. A minimum switching frequency and maximum duty cycle is guaranteed under all load conditions enabling the use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reduced volume of the passive components and better dynamic response. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple parallel modules. Simulations were conducted to verify the combined operation of both methods and measurements were performed on a 3 kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller.

Original language	English
Title of host publication	Proceedings of the 2010 International Power Electronics Conference (IPEC)
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	2822-2829
Number of pages	8
ISBN (Electronic)	978-1-4244-5393-1
ISBN (Print)	978-1-4244-5394-8
DOIs	https://doi.org/10.1109/IPEC.2010.5543891
Publication status	Published - 2010
Event	2008 International Conference on Power Electronics Conference (IPEC 2010) - Sapporo, Japan Duration: 21 Jun 2010 → 24 Jun 2010

Conference

Conference	2008 International Conference on Power Electronics Conference (IPEC 2010)
Abbreviated title	IPEC 2010
Country/Territory	Japan
City	Sapporo
Period	21/06/10 → 24/06/10

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10.1109/IPEC.2010.5543891

publishers verisonFinal published version, 2.1 MB

Cite this

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title = "Interleaved switching of parallel ZVS hysteresis current controlled inverters",

abstract = "A robust self-interleaving mechanism for parallel hysteresis current controlled inverters is proposed, with sustained switching under all load conditions. A fast interleaving technique that can be applied for normal load conditions is combined with a self-interleaving mechanism, which ensures correct switching during voltage clamping operation. A minimum switching frequency and maximum duty cycle is guaranteed under all load conditions enabling the use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reduced volume of the passive components and better dynamic response. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple parallel modules. Simulations were conducted to verify the combined operation of both methods and measurements were performed on a 3 kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller.",

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booktitle = "Proceedings of the 2010 International Power Electronics Conference (IPEC)",

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Schellekens, JM , Duarte, JL , Hendrix, MAM & Huisman, H 2010, Interleaved switching of parallel ZVS hysteresis current controlled inverters. in Proceedings of the 2010 International Power Electronics Conference (IPEC). Institute of Electrical and Electronics Engineers, Piscataway, pp. 2822-2829, 2008 International Conference on Power Electronics Conference (IPEC 2010), Sapporo, Japan, 21/06/10. https://doi.org/10.1109/IPEC.2010.5543891

Interleaved switching of parallel ZVS hysteresis current controlled inverters. / Schellekens, J.M.; Duarte, J.L.; Hendrix, M.A.M.; Huisman, H.

Proceedings of the 2010 International Power Electronics Conference (IPEC). Piscataway : Institute of Electrical and Electronics Engineers, 2010. p. 2822-2829.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Interleaved switching of parallel ZVS hysteresis current controlled inverters

AU - Schellekens, J.M.

AU - Duarte, J.L.

AU - Hendrix, M.A.M.

AU - Huisman, H.

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Y1 - 2010

N2 - A robust self-interleaving mechanism for parallel hysteresis current controlled inverters is proposed, with sustained switching under all load conditions. A fast interleaving technique that can be applied for normal load conditions is combined with a self-interleaving mechanism, which ensures correct switching during voltage clamping operation. A minimum switching frequency and maximum duty cycle is guaranteed under all load conditions enabling the use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reduced volume of the passive components and better dynamic response. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple parallel modules. Simulations were conducted to verify the combined operation of both methods and measurements were performed on a 3 kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller.

AB - A robust self-interleaving mechanism for parallel hysteresis current controlled inverters is proposed, with sustained switching under all load conditions. A fast interleaving technique that can be applied for normal load conditions is combined with a self-interleaving mechanism, which ensures correct switching during voltage clamping operation. A minimum switching frequency and maximum duty cycle is guaranteed under all load conditions enabling the use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reduced volume of the passive components and better dynamic response. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple parallel modules. Simulations were conducted to verify the combined operation of both methods and measurements were performed on a 3 kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller.

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DO - 10.1109/IPEC.2010.5543891

M3 - Conference contribution

SN - 978-1-4244-5394-8

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BT - Proceedings of the 2010 International Power Electronics Conference (IPEC)

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2008 International Conference on Power Electronics Conference (IPEC 2010)

Y2 - 21 June 2010 through 24 June 2010

ER -

Interleaved switching of parallel ZVS hysteresis current controlled inverters

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