Interconnect-aware mapping of applications to coarse-grain reconfigurable architectures

N. Bansal, Sumit Gupta, N.D. Dutt, A. Nicolau, R. Gupta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    11 Citations (Scopus)


    Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs.
    Original languageEnglish
    Title of host publicationField Programmable Logic and Applications (14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings)
    EditorsJ. Becker, M. Platzner, S. Vernalde
    Place of PublicationBerlin
    ISBN (Print)3-540-22989-2
    Publication statusPublished - 2004

    Publication series

    NameLecture Notes in Computer Science
    ISSN (Print)0302-9743


    Dive into the research topics of 'Interconnect-aware mapping of applications to coarse-grain reconfigurable architectures'. Together they form a unique fingerprint.

    Cite this