Integrating VLIW processors with a network on chip

J. Huisken

doi:10.1007/978-3-540-73625-7_2

Integrating VLIW processors with a network on chip

J. Huisken

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

Networks are a becoming a necessity to easily integrate multiple processors on a single chip. A crucial question here is whether it is good enough to reason about statistical performance as opposed to hard real-time performance constraints. Today’s processors often do not allow software design for hard real-time systems, caused by the design of the bus- and/or memory interfaces, thereby necessitating elaborate performance analysis through simulation.

In this presentation I will indicate what options a processor designer has, using Silicon Hive processor design tools, in specifying the interfaces and local memory sub-system in a processor. It allows a multitude of communication options to build either type of system: statistically bound or hard real-time bound performance.

Additionaly I will describe the multi-processor simulation and prototyping environment and touching on the processor design methodology.

Original language	English
Title of host publication	Embedded Computer Systems: Architectures, Modeling, and Simulation
Subtitle of host publication	7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007. Proceedings
Place of Publication	Berlin
Publisher	Springer
Chapter	2
Pages	2-2
Number of pages	1
ISBN (Electronic)	978-3-540-73625-7
ISBN (Print)	3-540-73622-0, 978-3-540-73622-6
DOIs	https://doi.org/10.1007/978-3-540-73625-7_2
Publication status	Published - 2007
Externally published	Yes

Publication series

Name	Lecture Notes in Computer Science (LNSC)
Volume	4599
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Access to Document

10.1007/978-3-540-73625-7_2

http://portal.acm.org/citation.cfm?id=1776200.1776203

Cite this

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title = "Integrating VLIW processors with a network on chip",

abstract = "Networks are a becoming a necessity to easily integrate multiple processors on a single chip. A crucial question here is whether it is good enough to reason about statistical performance as opposed to hard real-time performance constraints. Today{\textquoteright}s processors often do not allow software design for hard real-time systems, caused by the design of the bus- and/or memory interfaces, thereby necessitating elaborate performance analysis through simulation. In this presentation I will indicate what options a processor designer has, using Silicon Hive processor design tools, in specifying the interfaces and local memory sub-system in a processor. It allows a multitude of communication options to build either type of system: statistically bound or hard real-time bound performance. Additionaly I will describe the multi-processor simulation and prototyping environment and touching on the processor design methodology.",

author = "J. Huisken",

year = "2007",

doi = "10.1007/978-3-540-73625-7\_2",

language = "English",

isbn = "3-540-73622-0",

series = "Lecture Notes in Computer Science (LNSC)",

publisher = "Springer",

pages = "2--2",

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address = "Germany",

}

Integrating VLIW processors with a network on chip. / Huisken, J.
Embedded Computer Systems: Architectures, Modeling, and Simulation: 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007. Proceedings. Berlin: Springer, 2007. p. 2-2 (Lecture Notes in Computer Science (LNSC); Vol. 4599).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - Networks are a becoming a necessity to easily integrate multiple processors on a single chip. A crucial question here is whether it is good enough to reason about statistical performance as opposed to hard real-time performance constraints. Today’s processors often do not allow software design for hard real-time systems, caused by the design of the bus- and/or memory interfaces, thereby necessitating elaborate performance analysis through simulation. In this presentation I will indicate what options a processor designer has, using Silicon Hive processor design tools, in specifying the interfaces and local memory sub-system in a processor. It allows a multitude of communication options to build either type of system: statistically bound or hard real-time bound performance. Additionaly I will describe the multi-processor simulation and prototyping environment and touching on the processor design methodology.

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Integrating VLIW processors with a network on chip

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