Integrating hardware limitations in CAN schedulability analysis

D.A. Khan, R.J. Bril, N. Navet

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

24 Citations (Scopus)

Abstract

The existing schedulability analysis for the Controller Area Network (CAN) does not take into account that a CAN controller has finite buffer space to store outgoing messages and high priority messages may suffer from priority inversion if the buffers are already occupied by low priority messages. This gives rise to an additional delay for high priority messages, which, if not considered, may result in a deadline violation. In this paper, we explain the cause of this additional delay and extend the existing CAN schedulability analysis to integrate it. Finally, we suggest implementation guidelines that minimizes both the run-time CPU overhead and the additional delay due to priority inversion.
Original languageEnglish
Title of host publicationProceedings of the 8th IEEE International Workshop on Factory Communication Systems (WFCS 2010, Nancy, France, May 18-21, 2010)
PublisherInstitute of Electrical and Electronics Engineers
Pages207-210
ISBN (Print)978-1-4244-5460-0
DOIs
Publication statusPublished - 2010

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