Integrated test support features for multi-GHz DACs in 28nm CMOS

Patrick Quinn; G.I. Radulov; A.H.M. van Roermund

Integrated test support features for multi-GHz DACs in 28nm CMOS

Patrick Quinn
, G.I. Radulov
, A.H.M. van Roermund

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed.

Original language	English
Title of host publication	TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA
Number of pages	3
Publication status	Published - 13 Sept 2013
Event	TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits - Anaheim, United States Duration: 8 Sept 2013 → 13 Sept 2013

Conference

Conference	TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits
Country/Territory	United States
City	Anaheim
Period	8/09/13 → 13/09/13

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TVHSAC13_digest_of_quinn_paper

http://users-tima.imag.fr/rms/stratigopoulos/TVHSAC13_digest_of_papers.pdf

Cite this

@inproceedings{874ca8bb319d4b1aaadd6288e38001f9,

title = "Integrated test support features for multi-GHz DACs in 28nm CMOS",

abstract = "This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed. ",

author = "Patrick Quinn and G.I. Radulov and \{van Roermund\}, A.H.M.",

year = "2013",

month = sep,

day = "13",

language = "English",

booktitle = "TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA",

note = "TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits ; Conference date: 08-09-2013 Through 13-09-2013",

}

Quinn, P, Radulov, GI & van Roermund, AHM 2013, Integrated test support features for multi-GHz DACs in 28nm CMOS. in TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA. TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits, Anaheim, United States, 8/09/13. <http://users-tima.imag.fr/rms/stratigopoulos/TVHSAC13_digest_of_papers.pdf>

TY - GEN

T1 - Integrated test support features for multi-GHz DACs in 28nm CMOS

AU - Quinn, Patrick

AU - Radulov, G.I.

AU - van Roermund, A.H.M.

PY - 2013/9/13

Y1 - 2013/9/13

N2 - This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed.

AB - This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed.

M3 - Conference contribution

BT - TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA

T2 - TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits

Y2 - 8 September 2013 through 13 September 2013

ER -

Integrated test support features for multi-GHz DACs in 28nm CMOS

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