Integrated test support features for multi-GHz DACs in 28nm CMOS

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Abstract

This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed.
Original languageEnglish
Title of host publicationTVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA
Number of pages3
Publication statusPublished - 13 Sep 2013
EventTVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits - Anaheim, United States
Duration: 8 Sep 201313 Sep 2013

Conference

ConferenceTVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits
CountryUnited States
CityAnaheim
Period8/09/1313/09/13

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    Quinn, P., Radulov, G. I., & van Roermund, A. H. M. (2013). Integrated test support features for multi-GHz DACs in 28nm CMOS. In TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA http://users-tima.imag.fr/rms/stratigopoulos/TVHSAC13_digest_of_papers.pdf