This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed.
|Title of host publication||TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA|
|Number of pages||3|
|Publication status||Published - 13 Sept 2013|
|Event||TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits - Anaheim, United States|
Duration: 8 Sept 2013 → 13 Sept 2013
|Conference||TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits|
|Period||8/09/13 → 13/09/13|