We perform weight addition of four 10 Gbit/s channels employing a photonic integrated indium phosphide (InP) chip based on arrayed waveguide gratings (AWGs) and semiconductor optical amplifiers (SOAs) technology. Continuous weight tuning for positive and negative weight matrix numbers is demonstrated with a maximum reading error of 0.04. The utilized chip is already designed to perform cross-connectivity between two layers populated with 8 neurons each, for the complete integration of one input layer and one hidden layer for photonic multilayer perceptron neural network.
|Publication status||Published - 2018|
|Event||Conference in Cognitive Computing 2018: Merging Concepts with Hardware - Herrenhausen, Hannover, Germany|
Duration: 18 Dec 2018 → 20 Dec 2018
|Conference||Conference in Cognitive Computing 2018|
|Period||18/12/18 → 20/12/18|