Increasing the noise margin in organic circuits using deal gate field-effect transistors

M. Spijkman; E.C.P. Smits; P.W.M. Blom; D.M. Leeuw, de; Y. Bon Saint Come; S. Setayesh; E. Cantatore

doi:10.1063/1.2904624

Increasing the noise margin in organic circuits using deal gate field-effect transistors

M. Spijkman, E.C.P. Smits, P.W.M. Blom, D.M. Leeuw, de, Y. Bon Saint Come, S. Setayesh, E. Cantatore

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Abstract

Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by Vth=(Ct/Cb)Vtop gate, where Ct and Cb are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5 V. ©2008 American Institute of Physics

Original language	English
Article number	143304
Pages (from-to)	143304-1/3
Number of pages	3
Journal	Applied Physics Letters
Volume	92
Issue number	14
DOIs	https://doi.org/10.1063/1.2904624
Publication status	Published - 2008

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title = "Increasing the noise margin in organic circuits using deal gate field-effect transistors",

abstract = "Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by Vth=(Ct/Cb)Vtop gate, where Ct and Cb are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5 V. {\textcopyright}2008 American Institute of Physics",

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AU - Spijkman, M.

AU - Smits, E.C.P.

AU - Blom, P.W.M.

AU - Leeuw, de, D.M.

AU - Bon Saint Come, Y.

AU - Setayesh, S.

AU - Cantatore, E.

PY - 2008

Y1 - 2008

N2 - Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by Vth=(Ct/Cb)Vtop gate, where Ct and Cb are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5 V. ©2008 American Institute of Physics

AB - Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by Vth=(Ct/Cb)Vtop gate, where Ct and Cb are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5 V. ©2008 American Institute of Physics

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SP - 143304-1/3

JO - Applied Physics Letters

JF - Applied Physics Letters

IS - 14

M1 - 143304

ER -

Increasing the noise margin in organic circuits using deal gate field-effect transistors

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