Increasing the noise margin in organic circuits using deal gate field-effect transistors

M. Spijkman, E.C.P. Smits, P.W.M. Blom, D.M. Leeuw, de, Y. Bon Saint Come, S. Setayesh, E. Cantatore

Research output: Contribution to journalArticleAcademicpeer-review

55 Citations (Scopus)
89 Downloads (Pure)

Abstract

Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by Vth=(Ct/Cb)Vtop gate, where Ct and Cb are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5 V. ©2008 American Institute of Physics
Original languageEnglish
Article number143304
Pages (from-to)143304-1/3
Number of pages3
JournalApplied Physics Letters
Volume92
Issue number14
DOIs
Publication statusPublished - 2008

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