Abstract
Current technology-design optimization methodology focuses first on front-end devices and logic gates and then addresses back-end interconnects. But, such approach is no longer feasible for sub-nanometer technologies. Here, we present a circuit-level study where both devices and interconnects are co-optimized to improve energy efficiency. We investigate advanced CMOS technology with 7 nm FinFET devices, and Cu interconnects with various aspect ratios from 3, 5 to 10. Further, we explore the advantages of carbon nanotube (CNT) based circuits with CNT field-effect devices and interconnects. CNT technology can achieve better energy-delay-product with co-exploring front- and back-end co-optimization and paving the way for an intelligent circuit-/system-level design and technology co-optimization.
| Original language | English |
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| Title of host publication | 2019 IEEE International Electron Devices Meeting, IEDM 2019 |
| Publisher | Institute of Electrical and Electronics Engineers |
| ISBN (Electronic) | 9781728140315 |
| DOIs | |
| Publication status | Published - Dec 2019 |
| Externally published | Yes |
| Event | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: 7 Dec 2019 → 11 Dec 2019 |
Conference
| Conference | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 |
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| Country/Territory | United States |
| City | San Francisco |
| Period | 7/12/19 → 11/12/19 |
Bibliographical note
Funding Information:ACKNOWLEDGMENT This work has received funding from the EU Horizon 2020 CONNECT project under grant agreement No 688612.
Funding
ACKNOWLEDGMENT This work has received funding from the EU Horizon 2020 CONNECT project under grant agreement No 688612.
