Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node

Haotian Zheng; Alexios Balatsoukas-Stimming; Zizheng Cao; Ton Koonen

doi:10.1109/SiPS50750.2020.9195264

Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node

Haotian Zheng, Alexios Balatsoukas-Stimming, Zizheng Cao, Ton Koonen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1 /2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.

Original language	English
Title of host publication	2020 IEEE Workshop on Signal Processing Systems, SiPS 2020
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	6
ISBN (Electronic)	978-1-7281-8099-1
DOIs	https://doi.org/10.1109/SiPS50750.2020.9195264
Publication status	Published - Oct 2020
Event	34th IEEE Workshop on Signal Processing Systems, SiPS 2020 - Virtual, Coimbra, Portugal Duration: 20 Oct 2020 → 22 Oct 2020

Conference

Conference	34th IEEE Workshop on Signal Processing Systems, SiPS 2020
Country/Territory	Portugal
City	Virtual, Coimbra
Period	20/10/20 → 22/10/20

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10.1109/SiPS50750.2020.9195264

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@inproceedings{053bd970264d4c01b8c05f7d98651f71,

title = "Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node",

abstract = "Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1 /2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work. ",

author = "Haotian Zheng and Alexios Balatsoukas-Stimming and Zizheng Cao and Ton Koonen",

year = "2020",

month = oct,

doi = "10.1109/SiPS50750.2020.9195264",

language = "English",

booktitle = "2020 IEEE Workshop on Signal Processing Systems, SiPS 2020",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "34th IEEE Workshop on Signal Processing Systems, SiPS 2020 ; Conference date: 20-10-2020 Through 22-10-2020",

}

Zheng, H, Balatsoukas-Stimming, A , Cao, Z & Koonen, T 2020, Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node. in 2020 IEEE Workshop on Signal Processing Systems, SiPS 2020., 9195264, Institute of Electrical and Electronics Engineers, 34th IEEE Workshop on Signal Processing Systems, SiPS 2020, Virtual, Coimbra, Portugal, 20/10/20. https://doi.org/10.1109/SiPS50750.2020.9195264

Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node. / Zheng, Haotian; Balatsoukas-Stimming, Alexios ; Cao, Zizheng ; Koonen, Ton.

2020 IEEE Workshop on Signal Processing Systems, SiPS 2020. Institute of Electrical and Electronics Engineers, 2020. 9195264.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node

AU - Zheng, Haotian

AU - Balatsoukas-Stimming, Alexios

AU - Cao, Zizheng

AU - Koonen, Ton

PY - 2020/10

Y1 - 2020/10

N2 - Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1 /2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.

AB - Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1 /2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.

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U2 - 10.1109/SiPS50750.2020.9195264

DO - 10.1109/SiPS50750.2020.9195264

M3 - Conference contribution

AN - SCOPUS:85096782097

BT - 2020 IEEE Workshop on Signal Processing Systems, SiPS 2020

PB - Institute of Electrical and Electronics Engineers

T2 - 34th IEEE Workshop on Signal Processing Systems, SiPS 2020

Y2 - 20 October 2020 through 22 October 2020

ER -

Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node

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