Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node

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Abstract

Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1 /2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.

Original languageEnglish
Title of host publication2020 IEEE Workshop on Signal Processing Systems, SiPS 2020
PublisherInstitute of Electrical and Electronics Engineers
Number of pages6
ISBN (Electronic)978-1-7281-8099-1
DOIs
Publication statusPublished - Oct 2020
Event34th IEEE Workshop on Signal Processing Systems, SiPS 2020 - Virtual, Coimbra, Portugal
Duration: 20 Oct 202022 Oct 2020

Conference

Conference34th IEEE Workshop on Signal Processing Systems, SiPS 2020
CountryPortugal
CityVirtual, Coimbra
Period20/10/2022/10/20

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