Abstract
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1 /2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.
Original language | English |
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Title of host publication | 2020 IEEE Workshop on Signal Processing Systems, SiPS 2020 |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 6 |
ISBN (Electronic) | 978-1-7281-8099-1 |
DOIs | |
Publication status | Published - Oct 2020 |
Event | 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 - Virtual, Coimbra, Portugal Duration: 20 Oct 2020 → 22 Oct 2020 |
Conference
Conference | 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 |
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Country | Portugal |
City | Virtual, Coimbra |
Period | 20/10/20 → 22/10/20 |