Impact of process scaling on 1/f noise in advanced CMOS technologies

M. J. Knitel, P. H. Woerlee, A. J. Scholten, A. T.A. Zegers-Van Duijnhoven

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

34 Citations (Scopus)

Abstract

The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Svgate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Svgate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

Original languageEnglish
Title of host publication2000 IEEE International Electron Devices Meeting
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages463-466
Number of pages4
ISBN (Print)0-7803-6438-4
DOIs
Publication statusPublished - 1 Dec 2000
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 10 Dec 200013 Dec 2000

Conference

Conference2000 IEEE International Electron Devices Meeting
Country/TerritoryUnited States
CitySan Francisco, CA
Period10/12/0013/12/00

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