Impact of process scaling on 1/f noise in advanced CMOS technologies

M. J. Knitel; P. H. Woerlee; A. J. Scholten; A. T.A. Zegers-Van Duijnhoven

doi:10.1109/IEDM.2000.904356

Impact of process scaling on 1/f noise in advanced CMOS technologies

M. J. Knitel, P. H. Woerlee, A. J. Scholten, A. T.A. Zegers-Van Duijnhoven

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

42 Citations (Scopus)

Abstract

The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Sv_gate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Sv_gate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

Original language	English
Title of host publication	2000 IEEE International Electron Devices Meeting
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	463-466
Number of pages	4
ISBN (Print)	0-7803-6438-4
DOIs	https://doi.org/10.1109/IEDM.2000.904356
Publication status	Published - 1 Dec 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting, IEDM 2000 - San Francisco, United States Duration: 10 Dec 2000 → 13 Dec 2000

Conference

Conference	2000 IEEE International Electron Devices Meeting, IEDM 2000
Country/Territory	United States
City	San Francisco
Period	10/12/00 → 13/12/00

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10.1109/IEDM.2000.904356

Cite this

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title = "Impact of process scaling on 1/f noise in advanced CMOS technologies",

abstract = "The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Svgate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Svgate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.",

author = "Knitel, {M. J.} and Woerlee, {P. H.} and Scholten, {A. J.} and {Zegers-Van Duijnhoven}, {A. T.A.}",

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Knitel, MJ, Woerlee, PH, Scholten, AJ & Zegers-Van Duijnhoven, ATA 2000, Impact of process scaling on 1/f noise in advanced CMOS technologies. in 2000 IEEE International Electron Devices Meeting. Institute of Electrical and Electronics Engineers, Piscataway, pp. 463-466, 2000 IEEE International Electron Devices Meeting, IEDM 2000, San Francisco, California, United States, 10/12/00. https://doi.org/10.1109/IEDM.2000.904356

Impact of process scaling on 1/f noise in advanced CMOS technologies. / Knitel, M. J.; Woerlee, P. H.; Scholten, A. J. et al.

2000 IEEE International Electron Devices Meeting. Piscataway : Institute of Electrical and Electronics Engineers, 2000. p. 463-466.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Svgate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Svgate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

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Impact of process scaling on 1/f noise in advanced CMOS technologies

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