Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors

A. Bhoolokam; M. Nag; A. Chasin; S. Steudel; J. Genoe; G. Gelinck; G. Groeseneken; P. Heremans

doi:10.1109/ESSDERC.2014.6948820

Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors

A. Bhoolokam, M. Nag, A. Chasin, S. Steudel, J. Genoe, G. Gelinck, G. Groeseneken, P. Heremans

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.

Original language	English
Title of host publication	2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy
Editors	R. Bez
Place of Publication	Piscataway
Publisher	IEEE Computer Society
Pages	302-304
Number of pages	3
ISBN (Electronic)	978-1-4799-4376-0
ISBN (Print)	978-1-4799-4378-4
DOIs	https://doi.org/10.1109/ESSDERC.2014.6948820
Publication status	Published - 5 Nov 2014
Externally published	Yes
Event	44th European Solid-State Device Research Conference (ESSDERC 2014) - Palazzo del Casinò, Venezia, Italy Duration: 22 Sep 2014 → 26 Sep 2014 Conference number: 44 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6926646

Conference

Conference	44th European Solid-State Device Research Conference (ESSDERC 2014)
Abbreviated title	ESSDERC 2014
Country	Italy
City	Venezia
Period	22/09/14 → 26/09/14
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6926646

Keywords

a-IGZO
ESL
NBIS
PECVD
PVD

Access to Document

10.1109/ESSDERC.2014.6948820

Link to publication in Scopus

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Bhoolokam, A., Nag, M., Chasin, A., Steudel, S., Genoe, J., Gelinck, G., Groeseneken, G., & Heremans, P. (2014). Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors. In R. Bez (Ed.), 2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy (pp. 302-304). [6948820] IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2014.6948820

Bhoolokam, A. ; Nag, M. ; Chasin, A. ; Steudel, S. ; Genoe, J. ; Gelinck, G. ; Groeseneken, G. ; Heremans, P. / Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors. 2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy. editor / R. Bez. Piscataway : IEEE Computer Society, 2014. pp. 302-304

@inproceedings{5bfb49b5f7284541bbb29777d26753f4,

title = "Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors",

abstract = "In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.",

keywords = "a-IGZO, ESL, NBIS, PECVD, PVD",

author = "A. Bhoolokam and M. Nag and A. Chasin and S. Steudel and J. Genoe and G. Gelinck and G. Groeseneken and P. Heremans",

year = "2014",

month = nov,

day = "5",

doi = "10.1109/ESSDERC.2014.6948820",

language = "English",

isbn = "978-1-4799-4378-4",

pages = "302--304",

editor = "R. Bez",

booktitle = "2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casin{\`o}, Venezia Lido, Italy",

publisher = "IEEE Computer Society",

address = "United States",

note = "44th European Solid-State Device Research Conference (ESSDERC 2014), ESSDERC 2014 ; Conference date: 22-09-2014 Through 26-09-2014",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6926646",

}

Bhoolokam, A, Nag, M, Chasin, A, Steudel, S, Genoe, J, Gelinck, G, Groeseneken, G & Heremans, P 2014, Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors. in R Bez (ed.), 2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy., 6948820, IEEE Computer Society, Piscataway, pp. 302-304, 44th European Solid-State Device Research Conference (ESSDERC 2014), Venezia, Italy, 22/09/14. https://doi.org/10.1109/ESSDERC.2014.6948820

Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors. / Bhoolokam, A.; Nag, M.; Chasin, A.; Steudel, S.; Genoe, J.; Gelinck, G.; Groeseneken, G.; Heremans, P.

2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy. ed. / R. Bez. Piscataway : IEEE Computer Society, 2014. p. 302-304 6948820.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors

AU - Bhoolokam, A.

AU - Nag, M.

AU - Chasin, A.

AU - Steudel, S.

AU - Genoe, J.

AU - Gelinck, G.

AU - Groeseneken, G.

AU - Heremans, P.

N1 - Conference code: 44

PY - 2014/11/5

Y1 - 2014/11/5

N2 - In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.

AB - In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.

KW - a-IGZO

KW - ESL

KW - NBIS

KW - PECVD

KW - PVD

UR - http://www.scopus.com/inward/record.url?scp=84911980552&partnerID=8YFLogxK

U2 - 10.1109/ESSDERC.2014.6948820

DO - 10.1109/ESSDERC.2014.6948820

M3 - Conference contribution

AN - SCOPUS:84911980552

SN - 978-1-4799-4378-4

SP - 302

EP - 304

BT - 2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy

A2 - Bez, R.

PB - IEEE Computer Society

CY - Piscataway

T2 - 44th European Solid-State Device Research Conference (ESSDERC 2014)

Y2 - 22 September 2014 through 26 September 2014

ER -

Bhoolokam A, Nag M, Chasin A, Steudel S, Genoe J, Gelinck G et al. Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors. In Bez R, editor, 2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy. Piscataway: IEEE Computer Society. 2014. p. 302-304. 6948820 https://doi.org/10.1109/ESSDERC.2014.6948820