Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors

A. Bhoolokam, M. Nag, A. Chasin, S. Steudel, J. Genoe, G. Gelinck, G. Groeseneken, P. Heremans

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.

Original languageEnglish
Title of host publication2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy
EditorsR. Bez
Place of PublicationPiscataway
PublisherIEEE Computer Society
Pages302-304
Number of pages3
ISBN (Electronic)978-1-4799-4376-0
ISBN (Print)978-1-4799-4378-4
DOIs
Publication statusPublished - 5 Nov 2014
Externally publishedYes
Event44th European Solid-State Device Research Conference (ESSDERC 2014) - Palazzo del Casinò, Venezia, Italy
Duration: 22 Sept 201426 Sept 2014
Conference number: 44
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6926646

Conference

Conference44th European Solid-State Device Research Conference (ESSDERC 2014)
Abbreviated titleESSDERC 2014
Country/TerritoryItaly
CityVenezia
Period22/09/1426/09/14
Internet address

Keywords

  • a-IGZO
  • ESL
  • NBIS
  • PECVD
  • PVD

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