Abstract
IEEE Std P1838 is the DFT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DFT standard to include a flexible parallel port (FPP): An optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.
Original language | English |
---|---|
Title of host publication | Proceedings - 2018 23rd IEEE European Test Symposium, ETS 2018 |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 6 |
ISBN (Electronic) | 9781538637289 |
DOIs | |
Publication status | Published - 29 May 2018 |
Event | 23rd IEEE European Test Symposium, ETS 2018 - Bremen, Germany Duration: 28 May 2018 → 1 Jun 2018 |
Conference
Conference | 23rd IEEE European Test Symposium, ETS 2018 |
---|---|
Country/Territory | Germany |
City | Bremen |
Period | 28/05/18 → 1/06/18 |