IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)
174 Downloads (Pure)

Abstract

IEEE Std P1838 is the DFT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DFT standard to include a flexible parallel port (FPP): An optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.

Original languageEnglish
Title of host publicationProceedings - 2018 23rd IEEE European Test Symposium, ETS 2018
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages6
ISBN (Electronic)9781538637289
DOIs
Publication statusPublished - 29 May 2018
Event23rd IEEE European Test Symposium, ETS 2018 - Bremen, Germany
Duration: 28 May 20181 Jun 2018

Conference

Conference23rd IEEE European Test Symposium, ETS 2018
CountryGermany
CityBremen
Period28/05/181/06/18

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