Hybrid code-data prefetch-aware multiprocessor task graph scheduling.

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2 Citations (Scopus)


The ever increasing performance gap between processors and memories is one of the biggest performance bottlenecks for computer systems. In this paper, we propose a task scheduling technique that schedules an application, modeled with a task graph, on a multiprocessor system-on chip (MPSoC) that contains a limited on-chip memory. The proposed scheduling technique explores the trade-off between executing tasks in a code-driven (i.e. executing parallel tasks) or data-driven (i.e. executing pipelined tasks) manner to minimize the run-time of the application. Our static scheduler identifies those task sequences in which it is useful to use a code-driven execution and those task sequences that benefit from a data-driven execution. We extend the proposed technique to consider prefetching when choosing a suitable task order. The technique is implemented using an integer linear programming framework. To evaluate the effectiveness of the technique, we use an application from the multimedia domain and a synthetic task graph that is used in related work. Our experimental results show that our scheduler is able to reduce the run-time of an MP3 decoder application by 8% compared to a commonly used heuristic scheduler.
Original languageEnglish
Title of host publicationProceedings of the 2011 14th Euromicro Conference on Digital System Design, 31 August - 2 September , 2011, Oulu, Finland
EditorsParis Kitsos
Place of PublicationLos Alamitos
PublisherIEEE Computer Society
ISBN (Print)978-1-4577-1048-3
Publication statusPublished - 2011
Eventconference; DSS 11; 2011-08-31; 2011-09-02 -
Duration: 31 Aug 20112 Sept 2011


Conferenceconference; DSS 11; 2011-08-31; 2011-09-02
OtherDSS 11


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