HopliteRT*: Real-Time NoC for FPGA

Yilian Ribot Gonzalez (Corresponding author), Geoffrey Nelissen

Research output: Contribution to journalArticleAcademicpeer-review

6 Citations (Scopus)

Abstract

With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT; 2) change the network topology in order to improve the packets' worst-case traversal time (WCTT); 3) identify a flaw in the existing timing analysis of HopliteRT; and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least $2\times $ improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.

Original languageEnglish
Article number9211415
Pages (from-to)3650-3661
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume39
Issue number11
DOIs
Publication statusPublished - Nov 2020

Funding

Manuscript received April 17, 2020; revised June 17, 2020; accepted July 6, 2020. Date of publication October 2, 2020; date of current version October 27, 2020. This work was supported by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit under Grant UIDB/04234/2020. This article was presented in part at the International Conference on Embedded Software 2020 and appears as part of the ESWEEK-TCAD special issue. (Corresponding author: Yilian Ribot González.) Yilian Ribot González is with the CISTER Research Centre, ISEP, Polytechnic Institute of Porto, 4200-465 Porto, Portugal (e-mail: ribot@isep.ipp.pt).

FundersFunder number
CISTERUIDB/04234/2020
Portuguese Fundação para a Ciência e a Tecnologia
Ministério da Ciência, Tecnologia e Ensino Superior

    Keywords

    • Field programmable gate array
    • network-on-chips
    • real-time embedded systems
    • systems-on-chips
    • timing analysis

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