High-value MOS capacitor arrays in ultradeep trenches in silicon

F. Roozeboom, R. Elfrink, J. Verhoeven, J. Van den Meerakker, F. Holthuysen

Research output: Contribution to journalConference articlepeer-review

35 Citations (Scopus)


A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm2.

Original languageEnglish
Pages (from-to)581-584
Number of pages4
JournalMicroelectronic Engineering
Issue number1
Publication statusPublished - 1 Jan 2000
Externally publishedYes
Event25th International Conference on Micro- and Nano-Engineering - Rome, Italy
Duration: 21 Sept 199923 Sept 1999


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