A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm2.
|Number of pages||4|
|Publication status||Published - 1 Jan 2000|
|Event||25th International Conference on Micro- and Nano-Engineering - Rome, Italy|
Duration: 21 Sept 1999 → 23 Sept 1999