High-value MOS capacitor arrays in ultradeep trenches in silicon

F. Roozeboom; R. Elfrink; J. Verhoeven; J. Van den Meerakker; F. Holthuysen

doi:10.1016/S0167-9317(00)00383-X

High-value MOS capacitor arrays in ultradeep trenches in silicon

F. Roozeboom, R. Elfrink, J. Verhoeven, J. Van den Meerakker, F. Holthuysen

Research output: Contribution to journal › Conference article › peer-review

35 Citations (Scopus)

Abstract

A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm².

Original language	English
Pages (from-to)	581-584
Number of pages	4
Journal	Microelectronic Engineering
Volume	53
Issue number	1
DOIs	https://doi.org/10.1016/S0167-9317(00)00383-X
Publication status	Published - 1 Jan 2000
Externally published	Yes
Event	25th International Conference on Micro- and Nano-Engineering - Rome, Italy Duration: 21 Sept 1999 → 23 Sept 1999

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author = "F. Roozeboom and R. Elfrink and J. Verhoeven and {Van den Meerakker}, J. and F. Holthuysen",

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AU - Elfrink, R.

AU - Verhoeven, J.

AU - Van den Meerakker, J.

AU - Holthuysen, F.

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AB - A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm2.

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DO - 10.1016/S0167-9317(00)00383-X

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T2 - 25th International Conference on Micro- and Nano-Engineering

Y2 - 21 September 1999 through 23 September 1999

ER -

High-value MOS capacitor arrays in ultradeep trenches in silicon

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