A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 µm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.
|Title of host publication||Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego|
|Place of Publication||New York|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2000|
Compiet, J., Jong, de, P. W. T., Wambacq, P., Vandersteen, G., Donnay, S., Engels, M., & Bolsen, I. (2000). High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends. In Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego (pp. 135-140). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/SSMSD.2000.836461