High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

J. Compiet; P.W.T. Jong, de; P. Wambacq; G. Vandersteen; S. Donnay; M. Engels; I. Bolsen

doi:10.1109/SSMSD.2000.836461

High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

J. Compiet, P.W.T. Jong, de, P. Wambacq, G. Vandersteen, S. Donnay, M. Engels, I. Bolsen

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

1 Downloads (Pure)

Abstract

A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 µm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.

Original language	English
Title of host publication	Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego
Place of Publication	New York
Publisher	Institute of Electrical and Electronics Engineers
Pages	135-140
ISBN (Print)	0-7803-5975-5
DOIs	https://doi.org/10.1109/SSMSD.2000.836461
Publication status	Published - 2000

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10.1109/SSMSD.2000.836461

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Compiet, J., Jong, de, P. W. T., Wambacq, P., Vandersteen, G., Donnay, S., Engels, M., & Bolsen, I. (2000). High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends. In Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego (pp. 135-140). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/SSMSD.2000.836461

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title = "High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends",

abstract = "A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 µm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.",

author = "J. Compiet and {Jong, de}, P.W.T. and P. Wambacq and G. Vandersteen and S. Donnay and M. Engels and I. Bolsen",

year = "2000",

doi = "10.1109/SSMSD.2000.836461",

language = "English",

isbn = "0-7803-5975-5",

pages = "135--140",

booktitle = "Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

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Compiet, J, Jong, de, PWT, Wambacq, P, Vandersteen, G, Donnay, S, Engels, M & Bolsen, I 2000, High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends. in Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego. Institute of Electrical and Electronics Engineers, New York, pp. 135-140. https://doi.org/10.1109/SSMSD.2000.836461

High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends. / Compiet, J.; Jong, de, P.W.T.; Wambacq, P. et al.
Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego. New York: Institute of Electrical and Electronics Engineers, 2000. p. 135-140.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

AU - Compiet, J.

AU - Jong, de, P.W.T.

AU - Wambacq, P.

AU - Vandersteen, G.

AU - Donnay, S.

AU - Engels, M.

AU - Bolsen, I.

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AB - A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 µm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.

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DO - 10.1109/SSMSD.2000.836461

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SN - 0-7803-5975-5

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EP - 140

BT - Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego

PB - Institute of Electrical and Electronics Engineers

CY - New York

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Compiet J, Jong, de PWT, Wambacq P, Vandersteen G, Donnay S, Engels M et al. High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends. In Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego. New York: Institute of Electrical and Electronics Engineers. 2000. p. 135-140 doi: 10.1109/SSMSD.2000.836461

High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

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