A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 µm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.
|Title of host publication||Proc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego|
|Place of Publication||New York|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2000|