Hierarchy-aware and area-efficient test infrastructure design for core-based system chips

A. Sehgal, S.K. Goel, E.J. Marinissen, K. Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

11 Citations (Scopus)


Multiple levels of design hierarchy are common in current-generation system-on-chip (SOC) integrated circuits. However, most prior work on test access mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy. We investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios. In the first scenario, the wrapper and TAM implementation for the embedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider. In the second scenario, the wrapper and TAM architecture of the child cores embedded in the parent cores are implemented by the system integrator. Experimental results are presented for the ITC'02 SOC test benchmarks
Original languageEnglish
Title of host publicationProceedings Design, Automation and Test in Europe, 2006. DATE '06
Place of PublicationPIscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages6
ISBN (Print)978-3-9810801-1-7, 3-9810801-1-4
Publication statusPublished - 2006
Externally publishedYes
Event9th Conference on Design Automation & Test in Europe  (DATE 2006) - Munich, Germany
Duration: 6 Mar 200610 Mar 2006
Conference number: 9


Conference9th Conference on Design Automation & Test in Europe  (DATE 2006)
Abbreviated titleDATE 2006

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