Hardware task-status manager for an RTOS with FIFO communication

In this paper, we address the problem of improving the performance of real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute data-flow applications composed of multiple tasks, which communicate through First-In-First-Out (FIFO) queues. The tasks on each processor in the MPSoC are scheduled for execution by an instance of a Real-Time Operating System (RTOS). To improve performance, we propose a Hardware Task-Status Manager (HWTSM) block that reduces the Worst Case Execution Time (WCET) of the RTOS. The HWTSM is a Molen-style Custom Computing Unit (CCU), a coprocessor that determines the execution eligibility of tasks from FIFO-filling information. Furthermore, we propose a new processor-coprocessor execution model, denoted as parallel non-blocking. In this model the HWTSM execution overlaps with the execution of RTOS and user applications. The HWTSM is integrated into the existing CompSoC platform and this entire system is prototyped on a Xilinx XC5VFX130T FPGA chip. We experiment with two types of applications running in software, i.e., synthetic and real. With the synthetic applications, the results indicate a WCET reduction of the RTOS between 1.1 and 3.0 times. For each one of the real applications - JPEG and H.264 decoders, the experimental results indicate a WCET reduction of the RTOS by 1.3 and 1.6 times, respectively. The overall system performance gain vary from from 0.9% to 13.3% for synthetic applications, from 2.3% to 4.6% for the JPEG decoder, and from 3.8% to 7.5% for the H.264 decoder.