Hardware synthesis for reconfigurable heterogeneous pipelined accelerators.

L. Jozwiak, A.U. Douglas

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

9 Citations (Scopus)
92 Downloads (Pure)

Abstract

This paper discusses a method of hardware synthesis for re-configurable heterogeneous pipelined accelerators and corresponding EDA-tool that we developed. To evaluate the method and tool, we performed experiments using several representative image and signal processing cases. The experiments showed that our tool is able to automatically construct an optimized hardware that favorably compares to the hardware constructed by skilled human designers, but the tool does it several orders of magnitude faster than a human designer.
Original languageEnglish
Title of host publicationFifth International Conference on Information Technology: New Generations, 2008. ITNG 2008, 7-9 April 2008, Las vegas, Nevada
Place of PublicationLos Alamitos
PublisherIEEE Computer Society
Pages1123-1130
ISBN (Print)0-7695-3099-0
DOIs
Publication statusPublished - 2008

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