Hardware reuse in modern application-specific processors and accelerators

A. Solon Nery, L. Jozwiak, M. Lindwer, M. Cocco, N. Nedjah, F.M.G. Franca

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)


Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.
Original languageEnglish
Title of host publicationProceedings of the 14th Euromicro Conference on Digital System Design (DSD 2011), 31 August - 2 September 2011, Rio de Janeiro, Brazil
Place of PublicationLos Alamitos
PublisherIEEE Computer Society
ISBN (Print)978-1-4577-1048-3
Publication statusPublished - 2011
Event14th Euromicro Conference on Digital System Design (DSD 2011) - Oulu, Finland
Duration: 31 Aug 20112 Sept 2011
Conference number: 14


Conference14th Euromicro Conference on Digital System Design (DSD 2011)
Abbreviated titleDSD 2011
Other"Architectures, Methods and Tools"
Internet address


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