Hardware Implementation of Neural Self-Interference Cancellation

Yann Kurzo, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming (Corresponding author)

Research output: Contribution to journalArticleAcademicpeer-review

Abstract

In-band full-duplex systems can transmit and receive information simultaneously and on the same frequency band. However, due to the strong self-interference caused by the transmitter to its own receiver, the use of non-linear digital self-interference cancellation is essential. In this work, we describe a hardware architecture for a neural network-based non-linear self-interference (SI) canceller and we compare it with our own hardware implementation of a conventional polynomial based SI canceller. Our results show that, for the same SI cancellation performance, the neural network canceller has an 8.1times smaller area and requires 7.7times less power than the polynomial canceller. Moreover, the neural network canceller can achieve 7 dB more SI cancellation while still being 1.2times smaller than the polynomial canceller and only requiring 1.3times more power. These results show that NN-based methods applied to communications are not only useful from a performance perspective, but can also lead to order-of-magnitude implementation complexity reductions.

Original languageEnglish
Article number9086019
Pages (from-to)204-216
Number of pages13
JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Volume10
Issue number2
DOIs
Publication statusPublished - Jun 2020

Keywords

  • Accelerator architectures
  • neural networks (NNs)
  • Wireless communication

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