Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes

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Abstract

In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7,3) show that the proposed simplification has a small error-correcting performance degradation (0.005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6,3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz.
Original languageEnglish
Title of host publication2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2021)
PublisherInstitute of Electrical and Electronics Engineers
Number of pages5
ISBN (Electronic)978-1-7281-7605-5
DOIs
Publication statusPublished - 2021
Event2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2021) - Virtual conference, Toronto, Canada
Duration: 6 Jun 202111 Jun 2021
https://2021.ieeeicassp.org/

Conference

Conference2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2021)
Abbreviated titleICASSP 2021
Country/TerritoryCanada
CityToronto
Period6/06/2111/06/21
Internet address

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