Hardware design and implementation of a network-on-chip based load balancing swith fabric.

T. Karadeniz, L. Mhamdi, K.G.W. Goossens, J.J. Garcia-Luna-Aceves

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

12 Citations (Scopus)

Abstract

Network routers rely on an important hardware component, namely the switch fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A switch fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based switch fabric architecture and: 1) propose an FPGA based hardware implementation of the NOC switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.
Original languageEnglish
Title of host publicationProceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-7
DOIs
Publication statusPublished - 2012
Eventconference; ReConFig, Cancun, Mexico, December 2012 -
Duration: 1 Jan 2012 → …

Conference

Conferenceconference; ReConFig, Cancun, Mexico, December 2012
Period1/01/12 → …
OtherReConFig, Cancun, Mexico, December 2012

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Resource allocation
Switches
Hardware
Computer networks
Scheduling algorithms
Field programmable gate arrays (FPGA)
Throughput
Routers
Scheduling
Data storage equipment
Network-on-chip
Costs

Cite this

Karadeniz, T., Mhamdi, L., Goossens, K. G. W., & Garcia-Luna-Aceves, J. J. (2012). Hardware design and implementation of a network-on-chip based load balancing swith fabric. In Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico (pp. 1-7). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ReConFig.2012.6416753
Karadeniz, T. ; Mhamdi, L. ; Goossens, K.G.W. ; Garcia-Luna-Aceves, J.J. / Hardware design and implementation of a network-on-chip based load balancing swith fabric. Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico. Piscataway : Institute of Electrical and Electronics Engineers, 2012. pp. 1-7
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abstract = "Network routers rely on an important hardware component, namely the switch fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A switch fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based switch fabric architecture and: 1) propose an FPGA based hardware implementation of the NOC switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100{\%} throughput, ii) is at least as scalable as other architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.",
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Karadeniz, T, Mhamdi, L, Goossens, KGW & Garcia-Luna-Aceves, JJ 2012, Hardware design and implementation of a network-on-chip based load balancing swith fabric. in Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-7, conference; ReConFig, Cancun, Mexico, December 2012, 1/01/12. https://doi.org/10.1109/ReConFig.2012.6416753

Hardware design and implementation of a network-on-chip based load balancing swith fabric. / Karadeniz, T.; Mhamdi, L.; Goossens, K.G.W.; Garcia-Luna-Aceves, J.J.

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico. Piscataway : Institute of Electrical and Electronics Engineers, 2012. p. 1-7.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Karadeniz T, Mhamdi L, Goossens KGW, Garcia-Luna-Aceves JJ. Hardware design and implementation of a network-on-chip based load balancing swith fabric. In Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico. Piscataway: Institute of Electrical and Electronics Engineers. 2012. p. 1-7 https://doi.org/10.1109/ReConFig.2012.6416753