Hardware design and implementation of a network-on-chip based load balancing swith fabric.

T. Karadeniz, L. Mhamdi, K.G.W. Goossens, J.J. Garcia-Luna-Aceves

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

13 Citations (Scopus)


Network routers rely on an important hardware component, namely the switch fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A switch fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based switch fabric architecture and: 1) propose an FPGA based hardware implementation of the NOC switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.
Original languageEnglish
Title of host publicationProceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2012
Eventconference; ReConFig, Cancun, Mexico, December 2012 -
Duration: 1 Jan 2012 → …


Conferenceconference; ReConFig, Cancun, Mexico, December 2012
Period1/01/12 → …
OtherReConFig, Cancun, Mexico, December 2012


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