Guard-time design for symmetric synchronization in IEEE 802.15.4 time-slotted channel hopping

Time-Slotted Channel Hopping (TSCH) is considered as one of the most reliable MAC solutions for low- power wireless networking. In order to establish time-slotted communications, this technique requires all nodes to remain synchronized. The synchronization is continuously done through normal communications to compensate the clock drift between different nodes. In this paper, we present a detailed look into the behavior of the IEEE 802.15.4 PHY and MAC in terms of the synchronization task. We show that the relation between timeslot offsets provided by the standard leads to different synchronization error margins for positive and negative relative clock drifts. This is due to the time required for detection of ongoing transmissions at receivers. This may lead to the situation that two nodes are able to communicate in only one direction. Depending on which node is the source node, the available margin to compensate the relative clock drift is different. Accordingly, we provide new values for timeslot offsets to compensate positive and negative relative clock drifts equally. Simulation results confirm that the standard offsets reduce the performance of TSCH due to asymmetric synchronization error handling. The results also show that this negative effect is mitigated by using the new offsets provided in this paper.