GS/s AD conversion for broadband multi-stream reception

E.J.G. Janssen; A. Zanikopoulos; K. Doris; C. Nani; G. Weide, van der

doi:10.1007/978-1-4614-4587-6_4

GS/s AD conversion for broadband multi-stream reception

E.J.G. Janssen, A. Zanikopoulos, K. Doris, C. Nani, G. Weide, van der

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. It is used in a fully integrated direct sampling receiver for DOCSIS 3.0 including a digital multi-channel selection filter and a PLL. The ADC achieves an SNDR of 48.5 dB and a THD of less than - 58 dB at Nyquist with an input signal of 1.4Vpp - diff. It consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm2 in 65 nm CMOS.

Original language	English
Title of host publication	Proceedings of the 21st Workshop on Advances in Analog Circuit Design, AACD 2012, 27-29 March 2012, Valkenburg, The Netherlands
Editors	A.H.M. Roermund, van, A. Baschirotto, M. Steyaert
Place of Publication	Berlin
Publisher	Springer
Pages	51-71
ISBN (Print)	978-1-4614-4586-9
DOIs	https://doi.org/10.1007/978-1-4614-4587-6_4
Publication status	Published - 2012
Event	21st Workshop on Advances in Analog Circuit Design, AACD 2012 - Valkenburg, Netherlands Duration: 27 Mar 2012 → 29 Mar 2012 Conference number: 21

Conference

Conference	21st Workshop on Advances in Analog Circuit Design, AACD 2012
Country/Territory	Netherlands
City	Valkenburg
Period	27/03/12 → 29/03/12
Other	AACD 2012

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10.1007/978-1-4614-4587-6_4

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Janssen, E. J. G., Zanikopoulos, A., Doris, K., Nani, C., & Weide, van der, G. (2012). GS/s AD conversion for broadband multi-stream reception. In A. H. M. Roermund, van, A. Baschirotto, & M. Steyaert (Eds.), Proceedings of the 21st Workshop on Advances in Analog Circuit Design, AACD 2012, 27-29 March 2012, Valkenburg, The Netherlands (pp. 51-71). Springer. https://doi.org/10.1007/978-1-4614-4587-6_4

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title = "GS/s AD conversion for broadband multi-stream reception",

abstract = "In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. It is used in a fully integrated direct sampling receiver for DOCSIS 3.0 including a digital multi-channel selection filter and a PLL. The ADC achieves an SNDR of 48.5 dB and a THD of less than - 58 dB at Nyquist with an input signal of 1.4Vpp - diff. It consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm2 in 65 nm CMOS.",

author = "E.J.G. Janssen and A. Zanikopoulos and K. Doris and C. Nani and {Weide, van der}, G.",

year = "2012",

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note = "21st Workshop on Advances in Analog Circuit Design, AACD 2012 ; Conference date: 27-03-2012 Through 29-03-2012",

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Janssen, EJG, Zanikopoulos, A, Doris, K, Nani, C & Weide, van der, G 2012, GS/s AD conversion for broadband multi-stream reception. in AHM Roermund, van, A Baschirotto & M Steyaert (eds), Proceedings of the 21st Workshop on Advances in Analog Circuit Design, AACD 2012, 27-29 March 2012, Valkenburg, The Netherlands. Springer, Berlin, pp. 51-71, 21st Workshop on Advances in Analog Circuit Design, AACD 2012, Valkenburg, Netherlands, 27/03/12. https://doi.org/10.1007/978-1-4614-4587-6_4

GS/s AD conversion for broadband multi-stream reception. / Janssen, E.J.G.; Zanikopoulos, A.; Doris, K. et al.
Proceedings of the 21st Workshop on Advances in Analog Circuit Design, AACD 2012, 27-29 March 2012, Valkenburg, The Netherlands. ed. / A.H.M. Roermund, van; A. Baschirotto; M. Steyaert. Berlin: Springer, 2012. p. 51-71.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. It is used in a fully integrated direct sampling receiver for DOCSIS 3.0 including a digital multi-channel selection filter and a PLL. The ADC achieves an SNDR of 48.5 dB and a THD of less than - 58 dB at Nyquist with an input signal of 1.4Vpp - diff. It consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm2 in 65 nm CMOS.

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Janssen EJG, Zanikopoulos A, Doris K, Nani C, Weide, van der G. GS/s AD conversion for broadband multi-stream reception. In Roermund, van AHM, Baschirotto A, Steyaert M, editors, Proceedings of the 21st Workshop on Advances in Analog Circuit Design, AACD 2012, 27-29 March 2012, Valkenburg, The Netherlands. Berlin: Springer. 2012. p. 51-71 doi: 10.1007/978-1-4614-4587-6_4

GS/s AD conversion for broadband multi-stream reception

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