Abstract
This paper presents GreyHound, a new methodology to improve cell placement of logic netlists in standard design
ßows by utilizing the regular structure of datapath circuitry. Key features of the methodology are automatic extraction of
regular structures and utilization of regularity even after extensive logic optimization. The latter is important because
logic optimization tends to introduce signiÞcant non-regularities even though the underlying structural regularity is
largely preserved. In the proposed methodology, the structural regularity in the initial gate netlist produced by module
generators is extracted automatically. This results in alignment specs for the regular logic, which are used to drive the
subsequent placement of the netlist. After each customary iteration through placement and logic optimization, a logic
correspondence extractor is used to identify functional correspondences between the optimized and the original netlist.
Along these correspondences, the extracted structural alignment cell attributes are inherited from the initial to the
optimized circuit so that its cells can be aligned accordingly
Original language | English |
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Pages (from-to) | 111-135 |
Number of pages | 25 |
Journal | Integration : the VLSI Journal |
Volume | 25 |
Issue number | 2 |
DOIs | |
Publication status | Published - 1998 |