A technique for the automated synthesis of FSMs (finite state machines) from sets of interworkings (synchronous sequence charts) is described. This is useful for obtaining feedback from a set of scenarios during a system's definition phase or test phase. It is sound in the sense that the generated FSM only exhibits traces that correspond to one of the interworkings from the given set. It preserves deadlock freedom in the sense that no behaviours are lost. The concrete syntax of SDL is used to represent the resulting FSMs.