Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

Y. V. Ponomarev, C. Salm, J. Schmitz, P. H. Woerlee, P. A. Stolk, D. J. Gravesteijn

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

31 Citations (Scopus)

Abstract

We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si0.8Ge0.2 gates.

Original languageEnglish
Title of host publication1997 International Electron Devices Meeting
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages829-832
Number of pages4
ISBN (Print)0-7803-4100-7
DOIs
Publication statusPublished - 1 Dec 1997
Externally publishedYes
Event1997 International Electron Devices Meeting - Washington, DC, USA
Duration: 7 Dec 199710 Dec 1997

Conference

Conference1997 International Electron Devices Meeting
CityWashington, DC, USA
Period7/12/9710/12/97

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