Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

Y. V. Ponomarev; C. Salm; J. Schmitz; P. H. Woerlee; P. A. Stolk; D. J. Gravesteijn

doi:10.1109/IEDM.1997.650509

Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

Y. V. Ponomarev, C. Salm, J. Schmitz, P. H. Woerlee, P. A. Stolk, D. J. Gravesteijn

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

33 Citations (Scopus)

Abstract

We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si_0.8Ge_0.2 gates.

Original language	English
Title of host publication	1997 International Electron Devices Meeting
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	829-832
Number of pages	4
ISBN (Print)	0-7803-4100-7
DOIs	https://doi.org/10.1109/IEDM.1997.650509
Publication status	Published - 1 Dec 1997
Externally published	Yes
Event	1997 IEEE International Electron Devices Meeting, IEDM 1997 - Washington, United States Duration: 7 Dec 1997 → 10 Dec 1997

Conference

Conference	1997 IEEE International Electron Devices Meeting, IEDM 1997
Abbreviated title	IEDM 1997
Country/Territory	United States
City	Washington
Period	7/12/97 → 10/12/97

Access to Document

10.1109/IEDM.1997.650509

Cite this

@inproceedings{bc49d10e2724474bb39574429769e9d4,

title = "Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology",

abstract = "We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si0.8Ge0.2 gates.",

author = "Ponomarev, {Y. V.} and C. Salm and J. Schmitz and Woerlee, {P. H.} and Stolk, {P. A.} and Gravesteijn, {D. J.}",

year = "1997",

month = dec,

day = "1",

doi = "10.1109/IEDM.1997.650509",

language = "English",

isbn = "0-7803-4100-7",

pages = "829--832",

booktitle = "1997 International Electron Devices Meeting",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "1997 IEEE International Electron Devices Meeting, IEDM 1997, IEDM 1997 ; Conference date: 07-12-1997 Through 10-12-1997",

}

Ponomarev, YV, Salm, C, Schmitz, J, Woerlee, PH, Stolk, PA & Gravesteijn, DJ 1997, Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology. in 1997 International Electron Devices Meeting. Institute of Electrical and Electronics Engineers, Piscataway, pp. 829-832, 1997 IEEE International Electron Devices Meeting, IEDM 1997, Washington, Washington, United States, 7/12/97. https://doi.org/10.1109/IEDM.1997.650509

Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology. / Ponomarev, Y. V.; Salm, C.; Schmitz, J. et al.
1997 International Electron Devices Meeting. Piscataway: Institute of Electrical and Electronics Engineers, 1997. p. 829-832.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

AU - Ponomarev, Y. V.

AU - Salm, C.

AU - Schmitz, J.

AU - Woerlee, P. H.

AU - Stolk, P. A.

AU - Gravesteijn, D. J.

PY - 1997/12/1

Y1 - 1997/12/1

N2 - We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si0.8Ge0.2 gates.

AB - We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si0.8Ge0.2 gates.

UR - http://www.scopus.com/inward/record.url?scp=84886448090&partnerID=8YFLogxK

U2 - 10.1109/IEDM.1997.650509

DO - 10.1109/IEDM.1997.650509

M3 - Conference contribution

AN - SCOPUS:84886448090

SN - 0-7803-4100-7

SP - 829

EP - 832

BT - 1997 International Electron Devices Meeting

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 1997 IEEE International Electron Devices Meeting, IEDM 1997

Y2 - 7 December 1997 through 10 December 1997

ER -

Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this