Gate sizing using a statistical delay model

E.T.A.F. Jacobs, M.R.C.M. Berkelaar

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Original languageEnglish
Title of host publicationProc. IEEE/International Workshop on Logic Synthesis - IWLS'99
EditorsF. Somenzi
PublisherUniversity of Colorado
Pages307-311
Publication statusPublished - 1999
Eventconference; Workshop Notes 1997 ACM/IEEE International Workshop on Logic Synthesis, IWLS'97, Tahoe City, CA, 19-21 May 1997 - Tahoe City, Canada
Duration: 19 May 199721 May 1997

Conference

Conferenceconference; Workshop Notes 1997 ACM/IEEE International Workshop on Logic Synthesis, IWLS'97, Tahoe City, CA, 19-21 May 1997
Abbreviated titleIWLS '97
CountryCanada
CityTahoe City
Period19/05/9721/05/97
OtherWorkshop Notes 1997 ACM/IEEE International Workshop on Logic Synthesis, IWLS'97, Tahoe City, CA, 19-21 May 1997

Cite this

Jacobs, E. T. A. F., & Berkelaar, M. R. C. M. (1999). Gate sizing using a statistical delay model. In F. Somenzi (Ed.), Proc. IEEE/International Workshop on Logic Synthesis - IWLS'99 (pp. 307-311). University of Colorado.