Future of GPGPU micro-architectural parameters

C. Nugteren, G.J.W. Braak, van den, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)
1 Downloads (Pure)

Abstract

As graphics processing units (GPUs) are becoming increasingly popular for general purpose workloads (GPGPU), the question arises how such processors will evolve architecturally in the near future. In this work, we identify and discuss trade-offs for three GPU architecture parameters: active thread count, compute-memory ratio, and cluster and warp sizing. For each parameter, we propose changes to improve GPU design, keeping in mind trends such as dark silicon and the increasing popularity of GPGPU architectures. A key-enabler is dynamism and workload-adaptiveness, enabling among others: dynamic register file sizing, latency aware scheduling, roofline-aware DVFS, run-time cluster fusion, and dynamic warp sizing.
Original languageEnglish
Title of host publicationProceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 18-22 March 2013, Grenoble, France
Place of PublicationGrenoble
PublisherInstitute of Electrical and Electronics Engineers
Pages392-395
DOIs
Publication statusPublished - 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013) - Grenoble, France
Duration: 18 Mar 201322 Mar 2013
Conference number: 16
https://www.date-conference.com/date13/

Conference

Conference16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013)
Abbreviated titleDATE 2013
CountryFrance
CityGrenoble
Period18/03/1322/03/13
Other
Internet address

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