Abstract
This paper presents a two-stage fully integrated 60 GHz differential Low Noise Amplifier implemented in a TSMC bulk CMOS 65 nm technology. Implementation of a voltage-voltage feedback enables the neutralization of the Miller capacitance and the achievement of flat gain with a deviation of ± 0.25 dB over the entire 6 GHz bandwidth. It features a transducer gain (Gt) of 10 dB along with a noise figure (NF) of 3.8 dB, NFmin of 3.7 dB and a constant delay time. IIP3 is 4 dBm. It consumes 35 mW from a 1.2 V supply and only occupies 330 x 170 µm.
Original language | English |
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Title of host publication | Proceedings of 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF 2010), 11-13 January 2010, New Orleans, Louisiana |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 124-127 |
ISBN (Print) | 978-1-4244-5456-3 |
DOIs | |
Publication status | Published - 2010 |
Event | conference; SIRF 2010 - Duration: 1 Jan 2010 → … |
Conference
Conference | conference; SIRF 2010 |
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Period | 1/01/10 → … |
Other | SIRF 2010 |