FPGA implementation of HEVC intra prediction using high-level synthesis

Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/ICCE-Berlin.2016.7684745

FPGA implementation of HEVC intra prediction using high-level synthesis

Ercan Kalali, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

10 Citations (Scopus)

Abstract

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is proposed. The proposed HEVC intra prediction hardware, in the worst case, can process 35 full HD (1920×1080) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

Original language	English
Title of host publication	2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)
Publisher	Institute of Electrical and Electronics Engineers
Pages	163-166
Number of pages	4
ISBN (Electronic)	978-1-5090-2096-6
DOIs	https://doi.org/10.1109/ICCE-Berlin.2016.7684745
Publication status	Published - 27 Oct 2016
Externally published	Yes
Event	6th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2016 - Berlin, Germany Duration: 5 Sept 2016 → 7 Sept 2016 Conference number: 6

Conference

Conference	6th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2016
Abbreviated title	ICCE-Berlin 2016
Country/Territory	Germany
City	Berlin
Period	5/09/16 → 7/09/16

Keywords

FPGA
HEVC
HLS
Intra Prediction

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10.1109/ICCE-Berlin.2016.7684745

Cite this

@inproceedings{bc185abf02a04ef1a04ebdffd80acba1,

title = "FPGA implementation of HEVC intra prediction using high-level synthesis",

abstract = "Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is proposed. The proposed HEVC intra prediction hardware, in the worst case, can process 35 full HD (1920×1080) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.",

keywords = "FPGA, HEVC, HLS, Intra Prediction",

author = "Ercan Kalali and Ilker Hamzaoglu",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 6th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2016 , ICCE-Berlin 2016 ; Conference date: 05-09-2016 Through 07-09-2016",

year = "2016",

month = oct,

day = "27",

doi = "10.1109/ICCE-Berlin.2016.7684745",

language = "English",

pages = "163--166",

booktitle = "2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Kalali, E & Hamzaoglu, I 2016, FPGA implementation of HEVC intra prediction using high-level synthesis. in 2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)., 7684745, Institute of Electrical and Electronics Engineers, pp. 163-166, 6th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2016 , Berlin, Germany, 5/09/16. https://doi.org/10.1109/ICCE-Berlin.2016.7684745

FPGA implementation of HEVC intra prediction using high-level synthesis. / Kalali, Ercan; Hamzaoglu, Ilker.
2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin). Institute of Electrical and Electronics Engineers, 2016. p. 163-166 7684745.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - FPGA implementation of HEVC intra prediction using high-level synthesis

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

N1 - Conference code: 6

PY - 2016/10/27

Y1 - 2016/10/27

N2 - Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is proposed. The proposed HEVC intra prediction hardware, in the worst case, can process 35 full HD (1920×1080) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

AB - Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is proposed. The proposed HEVC intra prediction hardware, in the worst case, can process 35 full HD (1920×1080) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

KW - FPGA

KW - HEVC

KW - HLS

KW - Intra Prediction

UR - https://www.scopus.com/pages/publications/84994853830

U2 - 10.1109/ICCE-Berlin.2016.7684745

DO - 10.1109/ICCE-Berlin.2016.7684745

M3 - Conference contribution

SP - 163

EP - 166

BT - 2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

PB - Institute of Electrical and Electronics Engineers

T2 - 6th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2016

Y2 - 5 September 2016 through 7 September 2016

ER -

FPGA implementation of HEVC intra prediction using high-level synthesis

Abstract

Conference

Keywords

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