FPGA Implementation of Approximate Enumerative Sphere Shaping with Trellis Storage

Probabilistic amplitude shaping is a coded modulation technique for generating shaped inputs necessary to achieve the capacity of the Gaussian channel. One of these probabilistic amplitude shaping algorithms is enumerative sphere shaping.
In this work, we implement an approximate enumerative sphere shaper in hardware. Our implementation is fully pipelined and capable of producing one channel input symbol per clock cycle with only a single shaper instance. A throughput of over 1.4 Gb/s with a 738 MHz clock frequency is achieved for shaping blocklengths up to 64 symbols on the XCZU48DR FPGA. We also compare our implementation with four implementations from the literature in terms of resource utilization, throughput, and energy gap. The enumerative sphere shaping algorithm has a smaller gap to capacity than all competing algorithms for the same block length. Additionally, we show that our shaper achieves similar or better throughput per resource utilization compared to most of the competing algorithms.