FPGA based controller for large port count optical packet switches

N. Calabretta, A. Osers, J. Luo, H.J.S. Dorren

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

Abstract

We present an FPGA based label processor for in-band optical labels with a processing time independent of the number of label bits. This allows for implementing an optical packet switching architecture that scales to a large port count without compromising the latency. As proof-of-concept we have employed an FPGA board with 100 MHz clock to validate the operation of the label processor in a 160 Gb/s optical packet switching system. Experimental results show successful 3 label bits processing and 160 Gb/s packets switching with 1 dB power penalty and 470 ns of latency. Projections on the label processor performance by using more powerful FPGAs indicate that 60 label bits (260 optical addresses) can be processed within 31 ns. The low latency label processing technique can allow the implementation of intelligent systems for optimal routing of the packets in the optical domain.
Original languageEnglish
Title of host publicationProceedings of the 14th International Conference on Transparent Optical Networks (ICTON 2012), 2-5 July 2012 , Warwick, UK
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
ISBN (Print)978-1-4673-2227-0
DOIs
Publication statusPublished - 2012
Event14th International Conference on Transparent Optical Networks (ICTON 2012) - University of Warwick, Coventry, United Kingdom
Duration: 2 Jul 20125 Jul 2012
Conference number: 14
http://www.nit.eu/icton-2012

Conference

Conference14th International Conference on Transparent Optical Networks (ICTON 2012)
Abbreviated titleICTON 2012
CountryUnited Kingdom
CityCoventry
Period2/07/125/07/12
Internet address

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