Formal verification of sequential circuits using binary decision diagrams

C.A.J. Eijk, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Original languageEnglish
Title of host publicationProc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing
EditorsJ.P. Veen
Place of PublicationUtrecht, Netherlands
PublisherSTW Technology Foundation
Pages75-82
Publication statusPublished - 1995
Event1995 ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing - Mierlo, Netherlands
Duration: 23 Mar 199524 Mar 1995

Conference

Conference1995 ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing
Abbreviated titleProRISC/IEEE 1995
CountryNetherlands
CityMierlo
Period23/03/9524/03/95

Cite this

Eijk, van, C. A. J. (1995). Formal verification of sequential circuits using binary decision diagrams. In J. P. Veen (Ed.), Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing (pp. 75-82). STW Technology Foundation.