Formal specification of networks-on-chips: deadlock and evacuation

F. Verbeek; J. Schmaltz

doi:10.1109/DATE.2010.5457089

Formal specification of networks-on-chips: deadlock and evacuation

F. Verbeek
, J. Schmaltz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

Abstract

Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systems-on-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.

Original language	English
Title of host publication	Design, Automation and Test in Europe (DATE 2010, Dresden, Germany, March 8-12, 2010)
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	6
ISBN (Electronic)	978-3-9810801-6-2
ISBN (Print)	978-1-4244-7054-9
DOIs	https://doi.org/10.1109/DATE.2010.5457089
Publication status	Published - 2010
Externally published	Yes
Event	13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) - ICC, Dresden, Germany Duration: 8 Mar 2010 → 12 Mar 2010 Conference number: 13 https://www.date-conference.com/date10/

Conference

Conference	13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010)
Abbreviated title	DATE 2010
Country/Territory	Germany
City	Dresden
Period	8/03/10 → 12/03/10
Other
Internet address	https://www.date-conference.com/date10/

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10.1109/DATE.2010.5457089

Cite this

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title = "Formal specification of networks-on-chips: deadlock and evacuation",

abstract = "Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systems-on-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.",

author = "F. Verbeek and J. Schmaltz",

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language = "English",

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publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010), DATE 2010 ; Conference date: 08-03-2010 Through 12-03-2010",

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Verbeek, F & Schmaltz, J 2010, Formal specification of networks-on-chips: deadlock and evacuation. in Design, Automation and Test in Europe (DATE 2010, Dresden, Germany, March 8-12, 2010)., 5457089, Institute of Electrical and Electronics Engineers, Piscataway, 13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010), Dresden, Germany, 8/03/10. https://doi.org/10.1109/DATE.2010.5457089

Formal specification of networks-on-chips: deadlock and evacuation. / Verbeek, F.; Schmaltz, J.
Design, Automation and Test in Europe (DATE 2010, Dresden, Germany, March 8-12, 2010). Piscataway: Institute of Electrical and Electronics Engineers, 2010. 5457089.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

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T2 - 13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010)

AU - Verbeek, F.

AU - Schmaltz, J.

N1 - Conference code: 13

PY - 2010

Y1 - 2010

N2 - Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systems-on-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.

AB - Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systems-on-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.

U2 - 10.1109/DATE.2010.5457089

DO - 10.1109/DATE.2010.5457089

M3 - Conference contribution

SN - 978-1-4244-7054-9

BT - Design, Automation and Test in Europe (DATE 2010, Dresden, Germany, March 8-12, 2010)

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

Y2 - 8 March 2010 through 12 March 2010

ER -

Formal specification of networks-on-chips: deadlock and evacuation

Abstract

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