Abstract
Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systems-on-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.
| Original language | English |
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| Title of host publication | Design, Automation and Test in Europe (DATE 2010, Dresden, Germany, March 8-12, 2010) |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Number of pages | 6 |
| ISBN (Electronic) | 978-3-9810801-6-2 |
| ISBN (Print) | 978-1-4244-7054-9 |
| DOIs | |
| Publication status | Published - 2010 |
| Externally published | Yes |
| Event | 13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) - ICC, Dresden, Germany Duration: 8 Mar 2010 → 12 Mar 2010 Conference number: 13 https://www.date-conference.com/date10/ |
Conference
| Conference | 13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) |
|---|---|
| Abbreviated title | DATE 2010 |
| Country/Territory | Germany |
| City | Dresden |
| Period | 8/03/10 → 12/03/10 |
| Other | |
| Internet address |