Formal methods for the verification of digital circuits

C.A.J. Eijk, van

Research output: ThesisPhd Thesis 1 (Research TU/e / Graduation TU/e)

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Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • Department of Electrical Engineering
Supervisors/Advisors
  • Jess, Jochen, Promotor
  • Baeten, Jos, Promotor
  • Berkelaar, M.R.C.M., Copromotor
Award date9 Sep 1997
Place of PublicationEindhoven
Publisher
Print ISBNs90-386-0370-3
DOIs
Publication statusPublished - 1997

Cite this

Eijk, van, C. A. J. (1997). Formal methods for the verification of digital circuits. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR496632