Finfet sram cells with asymmetrical bitline access transistors for enhanced read stability

S.M. Salahuddin, V. Kursun, H. Jiao

Research output: Contribution to journalArticleAcademicpeer-review

6 Citations (Scopus)
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Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

Original languageEnglish
Pages (from-to)293-302
Number of pages10
JournalTransactions on Electrical and Electronic Materials
Issue number6
Publication statusPublished - 1 Dec 2015


  • Data stability
  • FinFET devices
  • Memory cache
  • SRAM cell
  • Underlap
  • Write voltage margin


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