Fault Tolerant FPGAs: where to spend the effort?

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Static Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in reallife applications, such as autonomous driving, high tech systems, and in space, where high dependability is a mandatory requirement. Since FPGA designs are stored in the Configuration Memory (CM) in SRAM-based FPGAs, they are very sensitive to Single Event Upsets (SEUs). Thus, adapting FPGA designs to make them more Fault Tolerant (FT) is extremely important. FT techniques introduce additional penalties in system parameters, like area, power consumption and performance. In order to tradeoff between the overhead introduced by FT techniques and system robustness, an accurate estimation of CM vulnerability to SEUs is needed. Many intrinsic error tolerant applications can tolerate in-exact output values to some degree. This paper shows how to exploit this property in making much cheaper FT FPGA designs with less overhead. For instance, our method can remove 51% of the area overhead for less than 0.048% output degradation, when considering a 32-bit FT adder FPGA design by applying Triple Modular Redundancy. We verify our results on various FPGA designs using a ZedBoard.

Original languageEnglish
Title of host publicationProceedings - Euromicro Conference on Digital System Design, DSD 2019
EditorsNikos Konofaos, Paris Kitsos
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)9781728128610
Publication statusPublished - 1 Aug 2019
Event22nd Euromicro Conference on Digital System Design, DSD 2019 - Kallithea, Kallithea, Chalkidiki, Greece
Duration: 28 Aug 201930 Aug 2019
Conference number: 22


Conference22nd Euromicro Conference on Digital System Design, DSD 2019
Abbreviated titleDSD 2019
CityKallithea, Chalkidiki
Internet address


  • Approximate Computing
  • Fault Tolerance
  • FPGA
  • Single Event Upset


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