@inproceedings{6d8fcc947aee42599fb0a5efc85e3b32,
title = "Faster and timing-attack resistant AES-GCM",
abstract = "We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous implementations, while simultaneously offering protection against timing attacks. In particular, it is the only cache-timing-attack resistant implementation offering competitive speeds for stream as well as for packet encryption: for 576-byte packets, we improve performance over previous bitsliced implementations by more than a factor of 2. We also report more than 30% improved speeds for lookup-table based Galois/Counter mode authentication, achieving 10.68 cycles/byte for authenticated encryption. Furthermore, we present the first constant-time implementation of AES-GCM that has a reasonable speed of 21.99 cycles/byte, thus offering a full suite of timing-analysis resistant software for authenticated encryption.",
author = "E. K{\"a}sper and P. Schwabe",
year = "2009",
doi = "10.1007/978-3-642-04138-9_1",
language = "English",
isbn = "978-3-642-04137-2",
series = "Lecture Notes in Computer Science",
publisher = "Springer",
pages = "1--17",
editor = "C. Clavier and K. Gaj",
booktitle = "Cryptographic Hardware and Embedded Systems - CHES 2009 (11th International Workshop, Lausanne, Switzerland, September 6-9, 2009. Proceedings)",
address = "Germany",
}