Fast time-domain simulation for reliable fault detection

Bratislav Tasić, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Theo G.J. Beelen, Roland Pulch

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

Original languageEnglish
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages301-306
Number of pages6
ISBN (Electronic)9783981537062
Publication statusPublished - 25 Apr 2016
Event19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
Duration: 14 Mar 201618 Mar 2016

Conference

Conference19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
CountryGermany
CityDresden
Period14/03/1618/03/16

Fingerprint

Fault detection
Networks (circuits)
Defects

Cite this

Tasić, B., Dohmen, J. J., Janssen, R., ter Maten, E. J. W., Beelen, T. G. J., & Pulch, R. (2016). Fast time-domain simulation for reliable fault detection. In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 (pp. 301-306). [7459327] Piscataway: Institute of Electrical and Electronics Engineers.
Tasić, Bratislav ; Dohmen, Jos J. ; Janssen, Rick ; ter Maten, E. Jan W. ; Beelen, Theo G.J. ; Pulch, Roland. / Fast time-domain simulation for reliable fault detection. Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Piscataway : Institute of Electrical and Electronics Engineers, 2016. pp. 301-306
@inproceedings{11a6115dca1f4bfcb910793d03b5d32d,
title = "Fast time-domain simulation for reliable fault detection",
abstract = "Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, {"}golden{"}, design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider {"}opens{"} (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.",
author = "Bratislav Tasić and Dohmen, {Jos J.} and Rick Janssen and {ter Maten}, {E. Jan W.} and Beelen, {Theo G.J.} and Roland Pulch",
year = "2016",
month = "4",
day = "25",
language = "English",
pages = "301--306",
booktitle = "Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Tasić, B, Dohmen, JJ, Janssen, R, ter Maten, EJW, Beelen, TGJ & Pulch, R 2016, Fast time-domain simulation for reliable fault detection. in Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016., 7459327, Institute of Electrical and Electronics Engineers, Piscataway, pp. 301-306, 19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14/03/16.

Fast time-domain simulation for reliable fault detection. / Tasić, Bratislav; Dohmen, Jos J.; Janssen, Rick; ter Maten, E. Jan W.; Beelen, Theo G.J.; Pulch, Roland.

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Piscataway : Institute of Electrical and Electronics Engineers, 2016. p. 301-306 7459327.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Fast time-domain simulation for reliable fault detection

AU - Tasić, Bratislav

AU - Dohmen, Jos J.

AU - Janssen, Rick

AU - ter Maten, E. Jan W.

AU - Beelen, Theo G.J.

AU - Pulch, Roland

PY - 2016/4/25

Y1 - 2016/4/25

N2 - Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

AB - Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

UR - http://www.scopus.com/inward/record.url?scp=84973660947&partnerID=8YFLogxK

UR - https://ieeexplore.ieee.org/document/7459327

M3 - Conference contribution

AN - SCOPUS:84973660947

SP - 301

EP - 306

BT - Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Tasić B, Dohmen JJ, Janssen R, ter Maten EJW, Beelen TGJ, Pulch R. Fast time-domain simulation for reliable fault detection. In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Piscataway: Institute of Electrical and Electronics Engineers. 2016. p. 301-306. 7459327