Fast time-domain simulation for reliable fault detection

Bratislav Tasić; Jos J. Dohmen; Rick Janssen; E. Jan W. ter Maten; Theo G.J. Beelen; Roland Pulch

Fast time-domain simulation for reliable fault detection

Bratislav Tasić, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Theo G.J. Beelen, Roland Pulch

Center for Analysis, Scientific Computing and Applications

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

Original language	English
Title of host publication	Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	301-306
Number of pages	6
ISBN (Electronic)	9783981537062
Publication status	Published - 25 Apr 2016
Event	19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016) - ICC, Dresden, Germany Duration: 14 Mar 2016 → 18 Mar 2016 Conference number: 19 https://www.date-conference.com/date16/

Conference

Conference	19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016)
Abbreviated title	DATE 2016
Country/Territory	Germany
City	Dresden
Period	14/03/16 → 18/03/16
Internet address	https://www.date-conference.com/date16/

Cite this

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title = "Fast time-domain simulation for reliable fault detection",

abstract = "Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, {"}golden{"}, design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider {"}opens{"} (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.",

author = "Bratislav Tasi{\'c} and Dohmen, {Jos J.} and Rick Janssen and {ter Maten}, {E. Jan W.} and Beelen, {Theo G.J.} and Roland Pulch",

year = "2016",

month = apr,

day = "25",

language = "English",

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booktitle = "Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016), DATE 2016 ; Conference date: 14-03-2016 Through 18-03-2016",

url = "https://www.date-conference.com/date16/",

}

Tasić, B, Dohmen, JJ, Janssen, R, ter Maten, EJW, Beelen, TGJ & Pulch, R 2016, Fast time-domain simulation for reliable fault detection. in Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016., 7459327, Institute of Electrical and Electronics Engineers, Piscataway, pp. 301-306, 19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016), Dresden, Germany, 14/03/16.

Fast time-domain simulation for reliable fault detection. / Tasić, Bratislav; Dohmen, Jos J.; Janssen, Rick et al.
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Piscataway: Institute of Electrical and Electronics Engineers, 2016. p. 301-306 7459327.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Fast time-domain simulation for reliable fault detection

AU - Tasić, Bratislav

AU - Dohmen, Jos J.

AU - Janssen, Rick

AU - ter Maten, E. Jan W.

AU - Beelen, Theo G.J.

AU - Pulch, Roland

N1 - Conference code: 19

PY - 2016/4/25

Y1 - 2016/4/25

N2 - Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

AB - Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

UR - http://www.scopus.com/inward/record.url?scp=84973660947&partnerID=8YFLogxK

UR - https://ieeexplore.ieee.org/document/7459327

M3 - Conference contribution

AN - SCOPUS:84973660947

SP - 301

EP - 306

BT - Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016)

Y2 - 14 March 2016 through 18 March 2016

ER -

Fast time-domain simulation for reliable fault detection

Abstract

Conference

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