Abstract
Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, ”golden”, design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider ”opens” (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden
solution and all faulty solutions are calculated over the same time step.
solution and all faulty solutions are calculated over the same time step.
Original language | English |
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Place of Publication | Eindhoven |
Publisher | Technische Universiteit Eindhoven |
Number of pages | 6 |
Publication status | Published - Mar 2016 |
Publication series
Name | CASA-report |
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Volume | 1603 |
ISSN (Print) | 0926-4507 |