Abstract
A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.
| Original language | English |
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| Title of host publication | 2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC) |
| Publisher | Institute of Electrical and Electronics Engineers |
| Number of pages | 6 |
| ISBN (Electronic) | 978-1-5386-6054-6 |
| ISBN (Print) | 978-1-5386-6055-3 |
| DOIs | |
| Publication status | Published - 26 Dec 2018 |
| Externally published | Yes |
| Event | 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018 - Shenzhen, China Duration: 4 Nov 2018 → 7 Nov 2018 |
Conference
| Conference | 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018 |
|---|---|
| Country/Territory | China |
| City | Shenzhen |
| Period | 4/11/18 → 7/11/18 |
Keywords
- compact model
- electro-thermal simulation
- power electronics reliability
- SiC MOSFET