Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping

Lorenzo Ceccarelli, Ramchandra Kotecha, Francesco Iannuzzo, Alan Mantooth

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.

Original languageEnglish
Title of host publication2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC)
PublisherInstitute of Electrical and Electronics Engineers
Number of pages6
ISBN (Electronic)978-1-5386-6054-6
ISBN (Print)978-1-5386-6055-3
DOIs
Publication statusPublished - 26 Dec 2018
Externally publishedYes
Event2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018 - Shenzhen, China
Duration: 4 Nov 20187 Nov 2018

Conference

Conference2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018
Country/TerritoryChina
CityShenzhen
Period4/11/187/11/18

Keywords

  • compact model
  • electro-thermal simulation
  • power electronics reliability
  • SiC MOSFET

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