Abstract
Vector DSPs are quite common in embedded SoCs used in compute-intensive domains such as imaging and wireless communication. To achieve short time-to-market, it is crucial to provide system architects and SW developers with fast and accurate instruction set simulators of such DSPs. To this end, a methodology for accelerating the simulation of vector instructions in vector DSPs is proposed. The acceleration is achieved by enabling automatic translation of the vector instructions in a given vector DSP binary into host SIMD instructions. The key advantage of the proposed methodology is its independence from the host architecture. Empirical evaluation, using a set of commercial vector DSPs, shows that the proposed methodology provides a 4x average reduction in simulation time of a vector instruction and a 2x average reduction in simulation time of a whole application.
Original language | English |
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Title of host publication | Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2018 |
Editors | Sander Stuijk |
Publisher | Association for Computing Machinery, Inc |
Pages | 47-53 |
Number of pages | 7 |
ISBN (Electronic) | 978-1-4503-5780-7 |
ISBN (Print) | 9781450357807 |
DOIs | |
Publication status | Published - 28 May 2018 |
Event | 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018) - St. Goar, Germany Duration: 28 May 2018 → 30 May 2018 |
Conference
Conference | 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018) |
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Country/Territory | Germany |
City | St. Goar |
Period | 28/05/18 → 30/05/18 |
Keywords
- Automatic Vectorization
- DSP Simulation
- Vector DSPs